The invention relates to a programmable reference circuit which, prior to programming, is in a first and after programming in a second logic state. The circuit comprises a flipflop-like circuit which in a non-programmed state is formed by two inverters in a feedback arrangement. A first inverter includes an active element and, arranged in series therewith a programmable element, which are arranged in series between two power supply terminals. An output of this first inverter is connected to an input of a second inverter, whose output supplies the reference voltage to be generated and is fed back to the input of the first inverter. The second inverter is, for example, a CMOS-inverter.
The invention further relates to an integrated circuit comprising a memory, in which for setting redundancy circuits for the substitution of defective rows and columns of memory cells a plurality of reference circuits are provided. Such an integrated circuit is described in a publication in the IEEE Journal of Solid State Circuits, Vol. 23, No. 5, October 1988, more specifically in chapter XI and FIG. 8.
A reference circuit of the type described above is known per se and is shown in FIG. 1. The reference circuit includes a first active element constituted by a PMOS-transistor P1 which is arranged in series with a programmable element, in this case a fuse F which together form a first inverter. The circuit further includes a second inverter assembled from a series arrangement of two PMOS-transistors P2 and P3 and two NMOS-transistors N1 and N2. The output L of the first inverter is connected to the control electrodes of the transistors P2, P3 and N1. The NMOS-transistor N2 receives a fixed voltage VREF (for example (V.sub.DD) at its control electrode to avoid voltage-stress on the transistor N1 as this transistor is a transistor of submicron dimensions. An NMOS-transistor N3 acting as a capacitance is connected between the supply voltage V.sub.SS and the output OUT of the second inverter while a PMOS-transistor P4 arranged as a capacitance is connected between the output L of the first inverter and the supply voltage V.sub.DD. The circuit operates as follows: as long as the fuse has not melted, it will be low-ohmic, so that after the supply voltage V.sub.DD has been switched on, charging of the capacitance constituted by the transistor P4 will be slower than charging of the capacitance constituted by the transistor N3, since both the junction point L and the junction point OUT will have zero potential after switch-on. The transistors P2 and P3 will be conductive, which causes the capacitance formed by transistor N3 to be charged. However, transistor P1 will also be conductive, but the junction point L will be kept at a low potential by the low-ohmic fuse F. The stable final state after switch-on of the circuit will then ultimately have a low level for the junction point L and a high logic level for the junction point OUT. However, after the fuse has melted, the junction point L will be charged to V.sub.DD so that the transistors P2 and P3 will be rendered non-conductive and the transistor N1 will start conducting. In response thereto the capacitance N3 will be discharged so that the output OUT will assume a low logic level. If now however the programmed circuit in which the fuse has melted, is switched off, then, due to the ever present leakage currents all the junction points in the circuit will in the end discharge. After the circuit has been switched on again, the junction point L and the junction point OUT have a low potential so that both transistor P1 and the transistors P2 and P3 will start to conduct. The two capacitances formed by the transistor P4 and N3 will not be in the charged state and be charged via the said transistors P1 and P2, P3, respectively. Now, however, it is uncertain which logic level the output OUT will assume, as charging of the capacitances is decisive for the ultimate logic state. So this state is determined by the RC-ratios of transistors P1 and capacitance P4 and the resistance formed by the transistors P2 and P3 and the capacitance N3. As in the IC-technology the tolerances of the different parameters cannot be controlled to perfection, it consequently remains uncertain what the ultimate logic state will be. For the case in which the capacitance N3 is charged faster than the capacitance P4 the transistor P1 will be forced out of the conductive state at an earlier instant than the transistor P2 and P3. This results in the junction point L not being charged anymore, and as a consequence thereof the transistors P2 and P3 are not rendered non-conductive and the junction point OUT is additionally charged until the logic high level. The foregoing procedure is unwanted as, after programming of the fuse, i.e. after the fuse has blown, the output must provide the desired logic low level. This situation is considered to be disadvantageous.